Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

Celý popis

Podrobná bibliografia

Vydané v:	IEEE access Ročník 7; s. 40674 - 40694
Hlavní autori:	Coutinho, Maria G. F., Torquato, Matheus F., Fernandes, Marcelo A. C.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Piscataway IEEE 2019 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Algorithms Artificial neural networks Computer architecture Deep learning Field programmable gate arrays FPGA Graphics processing units Hardware Machine learning Neural networks Reconfigurable hardware stacked sparse autoencoder systolic array Throughput
ISSN:	2169-3536, 2169-3536
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!