Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

Full description

Bibliographic Details

Published in:	IEEE access Vol. 7; pp. 40674 - 40694
Main Authors:	Coutinho, Maria G. F., Torquato, Matheus F., Fernandes, Marcelo A. C.
Format:	Journal Article
Language:	English
Published:	Piscataway IEEE 2019 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Artificial neural networks Computer architecture Deep learning Field programmable gate arrays FPGA Graphics processing units Hardware Machine learning Neural networks Reconfigurable hardware stacked sparse autoencoder systolic array Throughput
ISSN:	2169-3536, 2169-3536
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!