A Division-Free and Variable-Regularized LMS-Based Generalized Sidelobe Canceller for Adaptive Beamforming and Its Efficient Hardware Realization

This paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new...

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Bibliographic Details
Published in:IEEE access Vol. 6; pp. 64470 - 64485
Main Authors: Zhao, W., Lin, J. Q., Chan, S. C., So, H. K.-H.
Format: Journal Article
Language:English
Published: Piscataway IEEE 2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Adaptive arrays
adaptive beamformer
approximation
Array processing
Array signal processing
Beamforming
Convergence
Counting
Discrete cosine transform
division-free
FPGA
Gate arrays
Hardware
Least mean squares
Least mean squares algorithm
Linear arrays
Mathematical analysis
Matrix methods
Regularization
Sensor arrays
Sidelobes
Signal processing algorithms
Software algorithms
Statistical analysis
Steady state
Steering
variable regularization
variable step-size
ISSN:2169-3536, 2169-3536
Online Access:Get full text
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Summary:This paper proposes a new division-free generalized sidelobe canceller-based adaptive beamformer and its efficient hardware realization. A discrete cosine transform-based blocking matrix is proposed for uniform linear array to decorrelate the input so as to achieve a faster convergence speed. A new variable step-size least mean squares algorithm for complex input is proposed to further improve the convergence and the steady-state performance of the adaptive beamformer. Moreover, a variable regularization scheme is incorporated to mitigate possible signal cancellation due to possible mismatches in steering vector. Furthermore, a statistical analysis on the mean and mean squares convergence of the algorithm is performed and validated using Monte Carlo simulations. An efficient architecture of the proposed adaptive beamformer is also proposed for its real-time implementation. It employs a novel division-free approach by quantizing the normalization factor into a limited number of levels so that the division can be implemented using canonical signed digits, resulting in multiplier-less realization. The performance of the resultant division-free implementation can achieve similar convergence and steady-state performance as a conventional divider approach while achieving at least 21% less hardware resources and 26.85% higher operating speed in Xilinx Virtex7 (XC7VX330T) field programming gate array for an eight-sensor uniform linear array. Finally, the beam can be stabilized remarkably in only <inline-formula> <tex-math notation="LaTeX">1~\mu \text{s} </tex-math></inline-formula> at a system clock frequency of 124 MHz.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2018.2875409