Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC

The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an...

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Veröffentlicht in:	Chronic diseases and translational medicine Jg. 14; H. 6; S. 263 - 271
Hauptverfasser:	Mondal, Khokan, Das, Subhajit, Samanta, Tuhina
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Beijing The Institution of Engineering and Technology 01.11.2020 John Wiley & Sons, Inc
Schlagworte:	2D IC 2D integrated circuit interconnects 3D IC 3D integrated circuit interconnects accurate noise assessment Algorithms circuit design Circuits coupled RLC on‐chip interconnects coupling capacitance coupling inductance crosstalk crosstalk minimisation crosstalk noise model deep sub‐micron technology Design fringing capacitance guarding TSV termination high‐frequency operation incorrect noise estimation integrated circuit design integrated circuit interconnections integrated circuit modelling integrated circuit noise Interconnect Linear programming network routing Noise control Number systems overestimation resources rectilinear routing algorithm reduced coupling distance Research Article RLC circuits SPICE substrate resistivity three‐dimensional integrated circuits through‐silicon‐via time‐efficient method TSV structure unintentional noise Wire crosstalk noise model 3D IC 2D IC coupling capacitance through-silicon-via reduced coupling distance coupling inductance 3D integrated circuit interconnects 2D integrated circuit interconnects rectilinear routing algorithm integrated circuit design crosstalk minimisation three-dimensional integrated circuits coupled RLC on-chip interconnects SPICE integrated circuit noise network routing unintentional noise RLC circuits incorrect noise estimation integrated circuit interconnections guarding TSV termination deep sub-micron technology high-frequency operation accurate noise assessment overestimation resources time-efficient method crosstalk integrated circuit modelling substrate resistivity fringing capacitance TSV structure circuit design
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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Zusammenfassung:	The coupling capacitance and inductance of 2D and 3D integrated circuit (IC) interconnects in deep sub-micron technology has been increased due to reduced coupling distance in such a way that their magnitudes become comparable to the area and fringing capacitance of an interconnect. This leads to an increasing risk of failure due to unintentional noise and a need for accurate noise assessment. Incorrect noise estimation could either result in defects in circuit design if the design resources are understated or it will end up with a waste of overestimation resources. In this study, a crosstalk noise model for coupled RLC on-chip interconnects has been demonstrated. Subsequently, a novel time-efficient method is proposed to estimate and optimise the crosstalk noise precisely. The proposed method calculates coupling noise as well as optimises crosstalk noise, which has been validated using SPICE. Besides the estimation of crosstalk noise for 2D interconnect, this study also estimates the crosstalk noise for through-silicon-via (TSV), which is used to connect different dies vertically in a 3D IC. Under high-frequency operation, effects of signal rise time, TSV structure (height of the TSV), substrate resistivity and the guarding TSV termination on crosstalk noise have also been studied in this work.
Bibliographie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-8601 1751-861X 2095-882X 1751-861X 2589-0514
DOI:	10.1049/iet-cdt.2020.0010