Design and field programmable gate array implementation of cascade neural network based flux estimator for speed estimation in induction motor drives

This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives. The main focus of this study is the FPGA implementation of cascade NN based flux estimator. The major...

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Vydáno v:	IET electric power applications Ročník 11; číslo 1; s. 121 - 131
Hlavní autoři:	Venkadesan, Arunachalam, Himavathi, Srinivasan, Sedhuraman, Karthikeyan, Muthuramalingam, A
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	The Institution of Engineering and Technology 01.01.2017
Témata:	cascade neural network based flux estimator design cascade NN based flux estimator Cascades cost optimisation cost reduction Elliott function Estimators excitation function execution time reduction field programmable gate array implementation Field programmable gate arrays Flux FPGA implementation Hardware induction motor drives Induction motors layer multiplexing concept minimum bit precision Multiplexing neural nets Neural networks nonlinear activation function power engineering computing resource allocation resource utilization Spartan FPGA kit speed estimation cost reduction field programmable gate array implementation cost optimisation field programmable gate arrays layer multiplexing concept minimum bit precision induction motor drives speed estimation execution time reduction cascade NN based flux estimator power engineering computing Elliott function resource allocation cascade neural network based flux estimator design FPGA implementation excitation function Spartan FPGA kit nonlinear activation function resource utilization neural nets
ISSN:	1751-8660, 1751-8679, 1751-8679
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Shrnutí:	This study presents design and hardware implementation of cascade neural network (NN) based flux estimator using field programmable gate array (FPGA) for speed estimation in induction motor drives. The main focus of this study is the FPGA implementation of cascade NN based flux estimator. The major issues in FPGA implementation are optimisation of cost (resource) and execution time. A simple non-linear activation function called as Elliott function is used to reduce the execution time. To reduce the cost, and effectively utilise resource, the concept of layer multiplexing is adopted. The lowest bit precision needed for good performance of the estimator is identified and implemented. The proposed NN based flux estimator using simple excitation function and minimum bit precision is implemented using layer multiplexing technique. The designed estimator is tested on Spartan FPGA kit (3sd1800afg676-4) and the results obtained are presented.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23
ISSN:	1751-8660 1751-8679 1751-8679
DOI:	10.1049/iet-epa.2016.0550