Memory Considerations for Low Energy Ray Tracing

We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases L1...

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Vydáno v:	Computer graphics forum Ročník 34; číslo 1; s. 47 - 59
Hlavní autoři:	Kopta, D., Shkurko, K., Spjut, J., Brunvand, E., Davis, A.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Oxford Blackwell Publishing Ltd 01.02.2015
Témata:	Analysis Architecture architecture for accelerated graphics computing Computer graphics Computer memory Computer simulation Control systems Controllers Data processing Energy consumption Energy management graphics hardware hardware hardware, graphics hardware I.3.1 [Computer Graphics]: Hardware Architecture-Parallel Processing I.3.1 [Computer Graphics]: Hardware Architecture—Parallel Processing; I.3.7 [Computer Graphics]: Three‐Dimensional Graphics and Realism—Raytracing I.3.7 [Computer Graphics]: Three-Dimensional Graphics and Realism-Raytracing Pipelining (computers) Processors Random access memory ray casting/tracing hardware Ray tracing Simulation Studies Systems simulation
ISSN:	0167-7055, 1467-8659
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Popis
Shrnutí:	We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases L1 hit rates and reduces off‐chip memory energy substantially through better management of off‐chip memory access patterns. To evaluate this model, we augment our architectural simulator with a detailed memory system simulation that includes accurate control, timing and power models for memory controllers and off‐chip dynamic random‐access memory . These details change the results significantly over previous simulations that used a simpler model of off‐chip memory, indicating that this type of memory system simulation is important for realistic simulations that involve external memory. Secondly, we employ reconfigurable special‐purpose pipelines that are constructed dynamically under program control. These pipelines use shared execution units that can be configured to support the common compute kernels that are the foundation of the ray tracing algorithm. This reduces the overhead incurred by on‐chip memory and register accesses. These two synergistic features yield a ray tracing architecture that reduces energy by optimizing both on‐chip and off‐chip memory activity when compared to a more traditional approach. We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases L1 hit rates and reduces off‐chip memory energy substantially through better management of off‐chip memory access patterns. Secondly, we employ reconfigurable special‐purpose compute pipelines that are constructed dynamically under program control. These two synergistic features yield a ray tracing architecture that reduces energy by optimizing both on‐chip and off‐chip memory activity when compared to a more traditional approach. To evaluate this model, we augment our architectural simulator with a detailed off‐chip memory system simulation that includes accurate control, timing and power models for memory controllers and DRAM.
Bibliografie:	ark:/67375/WNG-HFLVFPWT-M istex:E5806BE9EDDD68F867375FFE6ED8A56DDD85A560 ArticleID:CGF12458 National Science Foundation - No. CNS-1017457 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 ObjectType-Article-1 ObjectType-Feature-2 content type line 23
ISSN:	0167-7055 1467-8659
DOI:	10.1111/cgf.12458