A hardware-oriented gold-washing adaptive vector quantizer and its VLSI architectures for image data compression

The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology Vol. 10; no. 8; pp. 1502 - 1513
Main Authors: MIAOU, Shaou-Gang, CHUNG, Wen-Song
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.12.2000
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Applied sciences
Architecture
Complexity
Computer architecture
Computers in experimental physics
Costs
Data compression
Decoding
Exact sciences and technology
Fundamental areas of phenomenology (including applications)
Hardware
Image coding
Image forming and processing
Image processing
Imaging and optical processing
Information, signal and communications theory
Instruments, apparatus, components and techniques common to several branches of physics and astronomy
Integrated circuits
Mathematical analysis
Optics
Physics
Pipelines
Signal processing
Strategy
Systolic arrays
Telecommunications and information theory
Vector quantization
Vectors (mathematics)
Very large scale integration
VLSI circuit
Vector quantization
Image processing
Pipelines
Data compression
Image databank
Gold coating
Decoding circuit
Encoding
Experimental study
Adaptive method
Implementation
Algorithms
Computer hardware
Linear antennas
Strategy
Quantifier
Systolic arrays
ISSN:1051-8215, 1558-2205
Online Access:Get full text
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Description
Summary:The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N+N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k+1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10/sup 6/ samples/s), respectively. These results are good enough for most of the practical image compression systems.
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ISSN:1051-8215
1558-2205
DOI:10.1109/76.889060