Digital Implementation of a Single Dynamical Node Reservoir Computer

Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements...

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Vydané v:IEEE transactions on circuits and systems. II, Express briefs Ročník 62; číslo 10; s. 977 - 981
Hlavní autori: Alomar, Miquel L., Soriano, Miguel C., Escalona-Morán, Miguel, Canals, Vincent, Fischer, Ingo, Mirasso, Claudio R., Rosselló, Jose L.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.10.2015
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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ISSN:1549-7747, 1558-3791
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Shrnutí:Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements and FPGA properties, namely, parallelism and adaptation. Here, we present an FPGA implementation of a conceptually simplified version of a recurrent NN based on a single dynamical node subject to delayed feedback. We show that this configuration is capable of successfully performing simple real-time temporal pattern classification and chaotic time-series prediction.
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ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2015.2458071