Digital Implementation of a Single Dynamical Node Reservoir Computer

Minimal hardware implementations of machine-learning techniques have been attracting increasing interest over the last decades. In particular, field-programmable gate array (FPGA) implementations of neural networks (NNs) are among the most appealing ones, given the match between system requirements...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Jg. 62; H. 10; S. 977 - 981
Hauptverfasser:	Alomar, Miquel L., Soriano, Miguel C., Escalona-Morán, Miguel, Canals, Vincent, Fischer, Ingo, Mirasso, Claudio R., Rosselló, Jose L.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.10.2015 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Artificial Neural Networks (ANN) Circuits Classification Computers Delays Digital computers Dynamical systems Dynamics Field programmable gate arrays field-programmable gate arrays (FPGA) Hardware hardware (HW) multiple signal classification neural network (NN) Neural networks pattern recognition Random access memory recurrent neural networks (RNN) Reservoirs time series prediction Training recurrent neural networks (RNN) hardware (HW) multiple signal classification field-programmable gate arrays (FPGAs) time-series prediction neural network (NN) Artificial neural networks (ANNs) pattern recognition
ISSN:	1549-7747, 1558-3791
Online-Zugang:	Volltext
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