Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition

This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both estimation and correction algorithms share the common derivative filter, which makes them possible to reduce the chip are...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 64; no. 6; pp. 1515 - 1528
Main Authors: Han Le Duc, Duc Minh Nguyen, Jabbour, Chadi, Desgreys, Patricia, Jamin, Olivier, Van Tam Nguyen
Format: Journal Article
Language:English
Published: New York IEEE 01.06.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Adaptive algorithms
Adaptive filters
Algorithms
All-digital feedforward calibration
Analog to digital conversion
Analog to digital converters
Calibration
Clocks
Correlation
Design engineering
Digital technology
Estimation
Feedforward neural networks
FPGA/ASIC implementation
Hardware description languages
polyphase filtering
Receivers
Sampling
Stability
subsampling and undersampling TIADCs
Technology utilization
Timing
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:This paper presents a low-power fully digital clock skew feedforward background calibration technique in sub-sampling Time-Interleaved Analog-to-Digital Converters (TIADCs). Both estimation and correction algorithms share the common derivative filter, which makes them possible to reduce the chip area. Furthermore, these algorithms use the polyphase filtering technique and do not use adaptive digital synthesis filters. Thus, the proposed calibration can be implemented on a moderate hardware cost with low power dissipation. The adopted feedforward technology eliminates the stability issues encountered with the adaptive technique. The Hardware Description Language (HDL) design of the proposed calibration is synthesized using a 28nm FD-SOI process for a 60dB SNR TIADC clocked at 2.7GHz. The calibration is designed for both baseband and sub-sampling TIADC applications. For subsampling TIADCs with the input at the first four Nyquist bands, the synthesized calibration system occupies 0.04mm2 of area and dissipates a total power of 33.2mW. For the baseband TIADC applications, it occupies 0.02mm2 and consumes 15.5mW.
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2016.2645978