Evaluating RISC-V Vector Instruction Set Architecture Extension with Computer Vision Workloads

Computer vision (CV) algorithms have been extensively used for a myriad of applications nowadays. As the multimedia data are generally well-formatted and regular, it is beneficial to leverage the massive parallel processing power of the underlying platform to improve the performances of CV algorithm...

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Vydáno v:Journal of computer science and technology Ročník 38; číslo 4; s. 807 - 820
Hlavní autoři: Li, Ruo-Shi, Peng, Ping, Shao, Zhi-Yuan, Jin, Hai, Zheng, Ran
Médium: Journal Article
Jazyk:angličtina
Vydáno: Singapore Springer Nature Singapore 01.07.2023
Springer
Springer Nature B.V
Témata:
Algorithms
Artificial Intelligence
Computer Science
Computer vision
Data Structures and Information Theory
Edge detection
Evaluation
Information Systems Applications (incl.Internet)
Instruction sets (computers)
Inventory control
Machine vision
Microprocessors
Multimedia
Multiprocessing
Parallel processing
Regular Paper
RISC
Software
Software Engineering
Theory of Computation
RISC-V vector extension
single instruction multiple data (SIMD)
OpenCV
computer vision
single instruction multiple data(SIMD)
ISSN:1000-9000, 1860-4749
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Shrnutí:Computer vision (CV) algorithms have been extensively used for a myriad of applications nowadays. As the multimedia data are generally well-formatted and regular, it is beneficial to leverage the massive parallel processing power of the underlying platform to improve the performances of CV algorithms. Single Instruction Multiple Data (SIMD) instructions, capable of conducting the same operation on multiple data items in a single instruction, are extensively employed to improve the efficiency of CV algorithms. In this paper, we evaluate the power and effectiveness of RISC-V vector extension (RV-V) on typical CV algorithms, such as Gray Scale, Mean Filter, and Edge Detection. By our examinations, we show that compared with the baseline OpenCV implementation using scalar instructions, the equivalent implementations using the RV-V (version 0.8) can reduce the instruction count of the same CV algorithm up to 24x, when processing the same input images. Whereas, the actual performances improvement measured by the cycle counts is highly related with the specific implementation of the underlying RV-V co-processor. In our evaluation, by using the vector co-processor (with eight execution lanes) of Xuantie C906, vector-version CV algorithms averagely exhibit up to 2.98x performances speedups compared with their scalar counterparts.
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ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-023-1266-6