Floating Gate Transistor‐Based Accurate Digital In‐Memory Computing for Deep Neural Networks
To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing,...
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| Vydané v: | Advanced intelligent systems Ročník 4; číslo 12 |
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| Hlavní autori: | , , , , , , , , , |
| Médium: | Journal Article |
| Jazyk: | English |
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Weinheim
John Wiley & Sons, Inc
01.12.2022
Wiley |
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| ISSN: | 2640-4567, 2640-4567 |
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| Abstract | To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing, which holds the key to DNNs, is proposed. Based on the proposed method, a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The proposed digital in‐memory computing method can achieve the central processing unit (CPU)‐equivalent precision with the same neural network architecture and parameters, different from the analogue or digital–analogue‐mixed in‐memory computing techniques. Based on the fabricated floating gate transistor‐based in‐memory computing chip, a hardware LeNet‐5 neural network is built. The chip achieves 96.25% accuracy on the full Modified National Institute of Standards and Technology database, which is the same as the result computed by the CPU with the same neural network architecture and parameters.
To improve the computing speed and energy efficiency of the deep neural network (DNN) applications, a digital in‐memory computing method for convolution computing is proposed and a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The recognition accuracy of the hardware neural network system is same as the software. |
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| AbstractList | To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in-memory computing with nonvolatile memory (NVM) is proposed to address the time-consuming and energy-hungry data shuttling issue. Herein, a digital in-memory computing method for convolution computing, which holds the key to DNNs, is proposed. Based on the proposed method, a floating gate transistor-based in-memory computing chip for accurate convolution computing with high parallelism is created. The proposed digital in-memory computing method can achieve the central processing unit (CPU)-equivalent precision with the same neural network architecture and parameters, different from the analogue or digital–analogue-mixed in-memory computing techniques. Based on the fabricated floating gate transistor-based in-memory computing chip, a hardware LeNet-5 neural network is built. The chip achieves 96.25% accuracy on the full Modified National Institute of Standards and Technology database, which is the same as the result computed by the CPU with the same neural network architecture and parameters. To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing, which holds the key to DNNs, is proposed. Based on the proposed method, a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The proposed digital in‐memory computing method can achieve the central processing unit (CPU)‐equivalent precision with the same neural network architecture and parameters, different from the analogue or digital–analogue‐mixed in‐memory computing techniques. Based on the fabricated floating gate transistor‐based in‐memory computing chip, a hardware LeNet‐5 neural network is built. The chip achieves 96.25% accuracy on the full Modified National Institute of Standards and Technology database, which is the same as the result computed by the CPU with the same neural network architecture and parameters. To improve the computing speed and energy efficiency of the deep neural network (DNN) applications, a digital in‐memory computing method for convolution computing is proposed and a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The recognition accuracy of the hardware neural network system is same as the software. |
| Author | Kang, Jinfeng Han, Runze Lin, Sheng Xiang, Yachen Hu, Hong Dong, Peiyan Shen, Wensheng Liu, Xiaoyan Huang, Peng Wang, Yanzhi |
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| Copyright | 2022 The Authors. Advanced Intelligent Systems published by Wiley‐VCH GmbH 2022. This work is published under http://creativecommons.org/licenses/by/4.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License. |
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| Snippet | To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed... To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in-memory computing with nonvolatile memory (NVM) is proposed... |
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| SubjectTerms | Accuracy Artificial neural networks Central processing units Chips (memory devices) Computer architecture Computer memory Convolution CPUs deep neural networks Energy efficiency flash memory floating gate transistors in-memory computing Internet of Things Neural networks parallel computing Parameters Semiconductor devices Software Transistors |
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| Title | Floating Gate Transistor‐Based Accurate Digital In‐Memory Computing for Deep Neural Networks |
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