Floating Gate Transistor‐Based Accurate Digital In‐Memory Computing for Deep Neural Networks

To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing,...

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Vydané v:Advanced intelligent systems Ročník 4; číslo 12
Hlavní autori: Han, Runze, Huang, Peng, Xiang, Yachen, Hu, Hong, Lin, Sheng, Dong, Peiyan, Shen, Wensheng, Wang, Yanzhi, Liu, Xiaoyan, Kang, Jinfeng
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Weinheim John Wiley & Sons, Inc 01.12.2022
Wiley
Predmet:
Accuracy
Artificial neural networks
Central processing units
Chips (memory devices)
Computer architecture
Computer memory
Convolution
CPUs
deep neural networks
Energy efficiency
flash memory
floating gate transistors
in-memory computing
Internet of Things
Neural networks
parallel computing
Parameters
Semiconductor devices
Software
Transistors
ISSN:2640-4567, 2640-4567
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Popis
Shrnutí:To improve the computing speed and energy efficiency of deep neural network (DNN) applications, in‐memory computing with nonvolatile memory (NVM) is proposed to address the time‐consuming and energy‐hungry data shuttling issue. Herein, a digital in‐memory computing method for convolution computing, which holds the key to DNNs, is proposed. Based on the proposed method, a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The proposed digital in‐memory computing method can achieve the central processing unit (CPU)‐equivalent precision with the same neural network architecture and parameters, different from the analogue or digital–analogue‐mixed in‐memory computing techniques. Based on the fabricated floating gate transistor‐based in‐memory computing chip, a hardware LeNet‐5 neural network is built. The chip achieves 96.25% accuracy on the full Modified National Institute of Standards and Technology database, which is the same as the result computed by the CPU with the same neural network architecture and parameters. To improve the computing speed and energy efficiency of the deep neural network (DNN) applications, a digital in‐memory computing method for convolution computing is proposed and a floating gate transistor‐based in‐memory computing chip for accurate convolution computing with high parallelism is created. The recognition accuracy of the hardware neural network system is same as the software.
Bibliografia:ObjectType-Article-1
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ISSN:2640-4567
2640-4567
DOI:10.1002/aisy.202200127