Hardware–software co-design of an iris recognition algorithm

This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algori...

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Vydáno v:IET information security Ročník 5; číslo 1; s. 60 - 68
Hlavní autoři: López, M., Daugman, J., Cantó, E.
Médium: Journal Article Publikace
Jazyk:angličtina
Vydáno: Stevenage John Wiley & Sons, Inc 01.03.2011
Témata:
Algorismes computacionals
Algorithms
Algorithms and architectures for advanced scientific computing
Architecture (computers)
Biometric recognition systems
Ciències de la salut
Ciències de la visió
Co-design
Computer programs
Computer software
Development
Disseny
Disseny SOC
Enginyeria de la telecomunicació
Enginyeria electrònica
Informàtica
Iris (Eye)
Iris (Ull)
Mathematical analysis
Medicina
Microelectrònica
Microprocessadors
Microprocessors
Oftalmologia
Optometria
Processament de dades
Processament del senyal
Programació
Programming
Reconeixement de formes
Running
Àrees temàtiques de la UPC
ISSN:1751-8709, 1751-8717
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Shrnutí:This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in <523 ms from an image of 640 × 480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.
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ISSN:1751-8709
1751-8717
DOI:10.1049/iet-ifs.2009.0267