Hardware–software co-design of an iris recognition algorithm

This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algori...

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Veröffentlicht in:IET information security Jg. 5; H. 1; S. 60 - 68
Hauptverfasser: López, M., Daugman, J., Cantó, E.
Format: Journal Article Verlag
Sprache:Englisch
Veröffentlicht: Stevenage John Wiley & Sons, Inc 01.03.2011
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ISSN:1751-8709, 1751-8717
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Zusammenfassung:This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in <523 ms from an image of 640 × 480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.
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ISSN:1751-8709
1751-8717
DOI:10.1049/iet-ifs.2009.0267