Hardware–software co-design of an iris recognition algorithm
This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algori...
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| Published in: | IET information security Vol. 5; no. 1; pp. 60 - 68 |
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| Main Authors: | , , |
| Format: | Journal Article Publication |
| Language: | English |
| Published: |
Stevenage
John Wiley & Sons, Inc
01.03.2011
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| Subjects: | |
| ISSN: | 1751-8709, 1751-8717 |
| Online Access: | Get full text |
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