Hardware–software co-design of an iris recognition algorithm
This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algori...
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| Vydané v: | IET information security Ročník 5; číslo 1; s. 60 - 68 |
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| Hlavní autori: | , , |
| Médium: | Journal Article Publikácia |
| Jazyk: | English |
| Vydavateľské údaje: |
Stevenage
John Wiley & Sons, Inc
01.03.2011
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| Predmet: | |
| ISSN: | 1751-8709, 1751-8717 |
| On-line prístup: | Získať plný text |
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| Shrnutí: | This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32-bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in <523 ms from an image of 640 × 480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture. |
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| Bibliografia: | SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 ObjectType-Article-1 ObjectType-Feature-2 content type line 23 |
| ISSN: | 1751-8709 1751-8717 |
| DOI: | 10.1049/iet-ifs.2009.0267 |