Decimator systolic arrays design space exploration for multirate signal processing applications

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained...

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Bibliographic Details
Published in:	IET circuits, devices & systems Vol. 13; no. 8; pp. 1232 - 1240
Main Authors:	Shoukry, Mohammed, Gebali, Fayez, Agathoklis, Panajotis
Format:	Journal Article
Language:	English
Published:	Stevenage The Institution of Engineering and Technology 01.11.2019 John Wiley & Sons, Inc
Subjects:	Algorithms antialiasing antialiasing FIR filter Commutators decimation factor decimator implementation decimator systolic arrays design space exploration dependence graph Design downsampler downsampling fastest design Field programmable gate arrays field-programmable gate array implementations filtering theory FIR filter coefficients FIR filters Fourier transforms Gate arrays known decimator designs multirate signal processing applications polyphase antialiasing filter polyphase design Power projection operations Research Article Scheduling Signal processing Space exploration systematic methodology systolic array design options systolic array structure Systolic arrays downsampler polyphase design systolic array structure field programmable gate arrays signal processing filtering theory decimator systolic arrays design space exploration decimator implementation systolic arrays systolic array design options multirate signal processing applications field-programmable gate array implementations projection operations antialiasing FIR filters systematic methodology dependence graph downsampling FIR filter coefficients fastest design decimation factor polyphase antialiasing filter known decimator designs antialiasing FIR filter
ISSN:	1751-858X, 1751-8598, 1751-8598
Online Access:	Get full text
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