Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 -12 and below. This requires decoding architectures that can take advantage of the unique characte...
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| Vydáno v: | IEEE transactions on circuits and systems. I, Regular papers Ročník 58; číslo 1; s. 98 - 111 |
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| Hlavní autoři: | , , , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
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New York
IEEE
01.01.2011
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1549-8328, 1558-0806 |
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| Abstract | Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 -12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board. |
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| AbstractList | Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of [Formula Omitted] and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board. Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 - 12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the bf H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board. Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 -12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board. |
| Author | Jingyu Kang Akella, Venkatesh Shu Lin Xiaoheng Chen |
| Author_xml | – sequence: 1 surname: Xiaoheng Chen fullname: Xiaoheng Chen email: xhchen@ucdavis.edu organization: Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA – sequence: 2 surname: Jingyu Kang fullname: Jingyu Kang email: jykang@ucdavis.edU organization: Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA – sequence: 3 surname: Shu Lin fullname: Shu Lin email: shulin@ucdavis.edu organization: Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA – sequence: 4 givenname: Venkatesh surname: Akella fullname: Akella, Venkatesh email: akella@ucdavis.edu organization: Dept. of Electr. & Comput. Eng., Univ. of California, Davis, Davis, CA, USA |
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| SubjectTerms | Alignment Architecture Bandwidth Codes Decoders Decoding Emulation Field programmable gate arrays field programmable logic array (FPGA) Folding Iterative decoding Low density parity check codes low-density parity-check (LDPC) decoder Mathematical analysis memory system optimization NASA normalized min-sum algorithm Optimization Parity check codes Programmable logic arrays quasi-cyclic low-density parity-check (QC-LDPC) codes Random access memory Throughput Vectors (mathematics) Very large scale integration very large scale integration (VLSI) implementation |
| Title | Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders |
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