Dynamically scalable dual-core pipelined processor

This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements t...

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Veröffentlicht in:International journal of electronics Jg. 102; H. 10; S. 1754 - 1764
Hauptverfasser: Kumar, Nishant, Aggrawal, Ekta, Rajawat, Arvind
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Abingdon Taylor & Francis 03.10.2015
Taylor & Francis LLC
Schlagworte:
Architecture (computers)
Data processing
Digital signal processors
dual core
Field programmable gate arrays
Microprocessors
Multiprogramming
parallel low data width
pipelined processor
Platforms
scalable
sequential high data width
Simulation
Streams
Switches
ISSN:0020-7217, 1362-3060
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Zusammenfassung:This article proposes design and architecture of a dynamically scalable dual-core pipelined processor. Methodology of the design is the core fusion of two processors where two independent cores can dynamically morph into a larger processing unit, or they can be used as distinct processing elements to achieve high sequential performance and high parallel performance. Processor provides two execution modes. Mode1 is multiprogramming mode for execution of streams of instruction of lower data width, i.e., each core can perform 16-bit operations individually. Performance is improved in this mode due to the parallel execution of instructions in both the cores at the cost of area. In mode2, both the processing cores are coupled and behave like single, high data width processing unit, i.e., can perform 32-bit operation. Additional core-to-core communication is needed to realise this mode. The mode can switch dynamically; therefore, this processor can provide multifunction with single design. Design and verification of processor has been done successfully using Verilog on Xilinx 14.1 platform. The processor is verified in both simulation and synthesis with the help of test programs. This design aimed to be implemented on Xilinx Spartan 3E XC3S500E FPGA.
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ISSN:0020-7217
1362-3060
DOI:10.1080/21681724.2014.996780