Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000

The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc....

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Veröffentlicht in:	IEEE transactions on circuits and systems for video technology Jg. 17; H. 10; S. 1336 - 1347
Hauptverfasser:	Zhang, Yi-Zhen, Xu, Chao, Wang, Wen-Tao, Chen, Liang-Bin
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY IEEE 01.10.2007 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Applied sciences Architecture Arithmetic Arithmetic coding Block codes Circuit properties Coders Coding, codes Context modeling Design engineering Digital video recorders Electric, optical and optoelectronic circuits Electronic circuits Electronics Embedded block coding with optimized truncation (EBCOT) Encoders Encoding Exact sciences and technology Field programmable gate arrays Hardware HDTV Image coding Imaging devices Information, signal and communications theory JPEG2000 Modules Parallel architectures Performance analysis Planes Recording and replay of audio and video signals Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal and communications theory Signal convertors Storage and reproduction of information Studies Telecommunications and information theory Video recorders VLSI Performance evaluation Block code High resolution Image processing High definition television Video signal Modeling Optimization Digital signal Image coding Ordering Embedded block coding with optimized truncation (EBCOT) High performance JPEG2000 Digital recorder VLSI Coding circuit Image compression Field programmable gate array Parallel architectures Algorithm Video recording Simulation Wavelet transformation Integrated circuit Arithmetic code Parallel connection Signal processing
ISSN:	1051-8215, 1558-2205
Online-Zugang:	Volltext
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