Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000

The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc....

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Bibliographic Details
Published in:IEEE transactions on circuits and systems for video technology Vol. 17; no. 10; pp. 1336 - 1347
Main Authors: Zhang, Yi-Zhen, Xu, Chao, Wang, Wen-Tao, Chen, Liang-Bin
Format: Journal Article
Language:English
Published: New York, NY IEEE 01.10.2007
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Applied sciences
Architecture
Arithmetic
Arithmetic coding
Block codes
Circuit properties
Coders
Coding, codes
Context modeling
Design engineering
Digital video recorders
Electric, optical and optoelectronic circuits
Electronic circuits
Electronics
Embedded block coding with optimized truncation (EBCOT)
Encoders
Encoding
Exact sciences and technology
Field programmable gate arrays
Hardware
HDTV
Image coding
Imaging devices
Information, signal and communications theory
JPEG2000
Modules
Parallel architectures
Performance analysis
Planes
Recording and replay of audio and video signals
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal and communications theory
Signal convertors
Storage and reproduction of information
Studies
Telecommunications and information theory
Video recorders
VLSI
Performance evaluation
Block code
High resolution
Image processing
High definition television
Video signal
Modeling
Optimization
Digital signal
Image coding
Ordering
Embedded block coding with optimized truncation (EBCOT)
High performance
JPEG2000
Digital recorder
VLSI
Coding circuit
Image compression
Field programmable gate array
Parallel architectures
Algorithm
Video recording
Simulation
Wavelet transformation
Integrated circuit
Arithmetic code
Parallel connection
Signal processing
ISSN:1051-8215, 1558-2205
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Summary:The algorithm of embedded block coding with optimization truncation (EBCOT) is one of the key techniques in JPEG2000 standard. The high-speed/performance hardware designs for EBCOT are critical to various high-resolution applications, such as digital cameras, digital video recorders, and HDTV, etc. This paper presents a detailed performance analysis for EBCOT Tier-1 and its bit plane parallel architecture design. By analyzing the bit plane parallel context modeling, we conclude that the difference between the output rate of context modeling module and that of arithmetic coding module degrades the performance of whole EBCOT parallel encoding. We propose two improved methods, referred to as data-pairs ordering (DPO) and flexible MQ (FMQ) coder. It solves the configuration problem between the parallel context modeling module and the sequent arithmetic coding module, takes full advantage of the bit plane parallel encoding technique, and improves the coding speed and efficiency of the EBCOT encoder significantly. The design of parallel EBCOT encoder is tested on the field-programmable gate array (FPGA) platform of Altera Company. The simulation results show that it can on average encode 54 million samples at 55-MHz working frequency. It is equivalent to encoding a 90006000 image per second or encoding 720 p (1280times720, 4:2:2) HDTV picture sequence nearly 30 frames per second. Compared with the conventional bit plane parallel architecture design, the proposed one can reduce execution time by 24%.
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ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2007.903789