Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root
In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies...
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| Veröffentlicht in: | Circuits, systems, and signal processing Jg. 40; H. 11; S. 5759 - 5772 |
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| Hauptverfasser: | , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
Springer US
01.11.2021
Springer Nature B.V |
| Schlagworte: | |
| ISSN: | 0278-081X, 1531-5878 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs. |
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| Bibliographie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 0278-081X 1531-5878 |
| DOI: | 10.1007/s00034-021-01738-1 |