Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root
In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies...
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| Veröffentlicht in: | Circuits, systems, and signal processing Jg. 40; H. 11; S. 5759 - 5772 |
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| Sprache: | Englisch |
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01.11.2021
Springer Nature B.V |
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| ISSN: | 0278-081X, 1531-5878 |
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| Abstract | In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs. |
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| AbstractList | In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs. |
| Author | Mopuri, Suresh Acharyya, Amit |
| Author_xml | – sequence: 1 givenname: Suresh orcidid: 0000-0002-4938-4995 surname: Mopuri fullname: Mopuri, Suresh organization: Department of Electrical Engineering, Indian Institute of Technology Hyderabad – sequence: 2 givenname: Amit orcidid: 0000-0002-5636-0676 surname: Acharyya fullname: Acharyya, Amit email: amit_acharyya@iith.ac.in organization: Department of Electrical Engineering, Indian Institute of Technology Hyderabad |
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| Cites_doi | 10.1023/A:1008110704586 10.1109/TVLSI.2017.2740343 10.1109/TCSII.2018.2878599 10.1109/TCSII.2009.2015386 10.1007/s00034-019-01277-w 10.1109/TCSI.2009.2025803 10.1109/ICCD.2009.5413129 10.1007/11533719_36 10.1109/TCSI.2018.2835822 10.1109/TCSII.2010.2050946 10.1109/TCSI.2019.2939720 10.11591/ijres.v1i1.440 10.1007/s11265-006-0029-2 10.1109/TVLSI.2019.2959847 10.1109/CECNet.2012.6201840 10.1109/WICOM.2010.5600929 10.1109/ICTSS.2013.6588110 10.1109/HIS.2009.27 10.1109/MWSCAS.2008.4616959 10.1117/12.831235 10.1109/WIMOB.2007.4390803 10.1109/WiCom.2008.534 |
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| References | Meher, Valls, Juang, Sridharan, Maharatna (CR6) 2009; 56 Ko, Yu, Wang (CR4) 2005 Mopuri, Acharyya (CR8) 2019; 66 Mopuri, Acharyya (CR7) 2017; 25 CR17 CR15 Wang, Ercegovac, Zheng (CR18) 2010; 57 Wang, Luo, Wang, Shen, Pan (CR19) 2020; 28 Acharyya, Maharatna, Al-Hashimi, Gunn (CR1) 2009; 56 Ercegovac, Muller (CR2) 2007; 49 CR13 CR12 CR23 Luo, Wang, Sun, Zha, Wang, Pan (CR5) 2018; 65 CR22 CR21 CR20 Mopuri, Bhardwaj, Acharyya (CR10) 2019; 66 Mopuri, Acharyya (CR9) 2020; 39 Volder (CR16) 2000; 25 Park, Kim (CR11) 2009; 2009 Sutikno, Jidin, Jidin, Idris (CR14) 2012; 1 Kahan, Powell, Iserles (CR3) 1987 1738_CR20 PK Meher (1738_CR6) 2009; 56 1738_CR22 1738_CR21 I Park (1738_CR11) 2009; 2009 1738_CR13 D Wang (1738_CR18) 2010; 57 1738_CR12 1738_CR23 S Mopuri (1738_CR9) 2020; 39 T Sutikno (1738_CR14) 2012; 1 1738_CR15 1738_CR17 S Mopuri (1738_CR7) 2017; 25 S Mopuri (1738_CR8) 2019; 66 Y Wang (1738_CR19) 2020; 28 Y Luo (1738_CR5) 2018; 65 JE Volder (1738_CR16) 2000; 25 KI Ko (1738_CR4) 2005 A Acharyya (1738_CR1) 2009; 56 MD Ercegovac (1738_CR2) 2007; 49 W Kahan (1738_CR3) 1987 S Mopuri (1738_CR10) 2019; 66 |
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| SubjectTerms | Circuits and Systems CMOS Complexity Computation Design engineering Digital computers Electrical Engineering Electronics and Microelectronics Engineering High speed Instrumentation Integrated circuits Methods Power consumption Principal components analysis Short Paper Signal processing Signal,Image and Speech Processing |
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