A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorith...

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Bibliographic Details
Published in:Electronics (Basel) Vol. 7; no. 7; p. 104
Main Authors: Hu, Xianghong, Zheng, Xin, Zhang, Shengshi, Cai, Shuting, Xiong, Xiaoming
Format: Journal Article
Language:English
Published: Basel MDPI AG 03.07.2018
Subjects:
Addition & subtraction
Algorithms
CMOS
Computer architecture
Consumption
Cryptography
Data storage
Design optimization
Digital signatures
Elliptic functions
Embedded systems
Gate counting
Hardware
International conferences
Multiplication
Multiplication & division
Synthesis
United States > US
China
Germany
ISSN:2079-9292, 2079-9292
Online Access:Get full text
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Summary:In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 μm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.
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ISSN:2079-9292
2079-9292
DOI:10.3390/electronics7070104