Algorithm-Hardware Codesign of Fast Parallel Round-Robin Arbiters

As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, wh...

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Vydané v:IEEE transactions on parallel and distributed systems Ročník 18; číslo 1; s. 84 - 95
Hlavní autori: Zheng, Si Qing, Yang, Mei
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.01.2007
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithm design and analysis
Algorithms
Arbiters
Arbitration
Binary trees
Circuits
circuits and systems
Delay
Design
Design engineering
Design of experiments
Hardware
High speed
Libraries
matching
parallel processing
Round robin
round-robin arbiter
Routers
Studies
switch scheduling
Switches
Time measurements
Timing
Wire
ISSN:1045-9219, 1558-2183
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Shrnutí:As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, which is specially designed for hardware implementation. We prove that our PRRA achieves round-robin fairness under all input patterns. We further propose an improved (IPRRA) design that reduces the timing of PRRA significantly. Simulation results with TSMC .18mum standard cell library show that PRRA and IPRRA can meet the timing requirement of a terabit 256 times 256 switch. Both PRRA and IPRRA are much faster and simpler than the programmable priority encoder (PPE), a well-known round-robin arbiter design. We also introduce an additional design which combines PRRA and IPRRA and provides trade-offs in gate delay, wire delay, and circuit area. With the binary tree structure and high performance, our designs are scalable for large N and useful for implementing schedulers for high-speed switches and routers
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ISSN:1045-9219
1558-2183
DOI:10.1109/TPDS.2007.253283