A Scalable and Modular Architecture for High-Performance Packet Classification

Packet classification is widely used as a core function for various applications in network infrastructure. With increasing demands in throughput, performing wire-speed packet classification has become challenging. Also the performance of today's packet classification solutions depends on the c...

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Veröffentlicht in:IEEE transactions on parallel and distributed systems Jg. 25; H. 5; S. 1135 - 1144
Hauptverfasser: Ganegedara, Thilan, Weirong Jiang, Prasanna, Viktor K.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.05.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Architecture
Architecture (computers)
Arrays
ASIC
Classification
Conversion
Field programmable gate arrays
firewall
FPGA
Hardware
hardware architectures
High speed
Memory management
Modular
network security
networking
Packet classification
Pipelines
Product introduction
router
State of the art
Throughput
Vectors
ISSN:1045-9219, 1558-2183
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Zusammenfassung:Packet classification is widely used as a core function for various applications in network infrastructure. With increasing demands in throughput, performing wire-speed packet classification has become challenging. Also the performance of today's packet classification solutions depends on the characteristics of rulesets. In this work, we propose a novel modular Bit-Vector (BV) based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA). We introduce an algorithm named StrideBV and modularize the BV architecture to achieve better scalability than traditional BV methods. Further, we incorporate range search in our architecture to eliminate ruleset expansion caused by range-to-prefix conversion. The post place-and-route results of our implementation on a state-of-the-art FPGA show that the proposed architecture is able to operate at 100+ Gbps for minimum size packets while supporting large rulesets up to 28 K rules using only the on-chip memory resources. Our solution is ruleset-feature independent , i.e. the above performance can be guaranteed for any ruleset regardless the composition of the ruleset.
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ISSN:1045-9219
1558-2183
DOI:10.1109/TPDS.2013.261