A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS

This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Bo...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 41; no. 1; pp. 256 - 264
Main Authors:	Hsu, S.K., Mathew, S.K., Anders, M.A., Zeydel, B.R., Oklobdzija, V.G., Krishnamurthy, R.K., Borkar, S.Y.
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01.01.2006 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	2's complement Adders Applied sciences Booth encoding Circuit properties Circuits Clocks CMOS CMOS technology Complement Compressors Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Encoding Exact sciences and technology flip-flop Flip-flops Integrated circuits Integrated circuits by function (including memories and processors) multiplier Multipliers Noise measurement Power measurement programmable logic array (PLA) Programmable logic arrays radix-4 reconfigurable Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Sleep sleep transistor Time measurement Transistors Trees Performance evaluation Scalability Clock 2's complement Wiring reconfigurable Low voltage radix-4 Coding Complementary MOS technology Booth encoding 16 bit Processor Programmable logic array MOS transistor Reconfigurable architectures Voltage mode Execution time programmable logic array (PLA) Arithmetic circuit Reactivation multiplier PMOS technology Bistable Adder Fan Integrated circuit Noise immunity Low-power electronics Voltage multipliers flip-flop sleep transistor
ISSN:	0018-9200, 1558-173X
Online Access:	Get full text
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Summary:	This paper describes a 16 /spl times/ 16 bit single-cycle 2's complement multiplier with a reconfigurable PLA control block fabricated in 90-nm dual-V/sub t/ CMOS technology, operating at 1 GHz, 9 mW (measured at 1.3 V, 50/spl deg/C). Optimally tiled compressor tree architecture with radix-4 Booth encoding, arrival-profile aware completion adder and low clock power write-port flip-flop circuits enable a dense layout occupying 0.03 mm/sup 2/ while simultaneously achieving: 1) low compressor tree fan-outs and wiring complexity; 2) low active leakage power of 540 /spl mu/W and high noise tolerance with all high-V/sub t/ usage; 3) ultra low standby-mode power of 75 /spl mu/W and fast wake-up time of <1 cycle using PMOS sleep transistors; 4) scalable multiplier performance up to 1.5 GHz, 32 mW measured at 1.95 V, 50/spl deg/C, and (v) low-voltage mode multiplier performance of 50 MHz, 79/spl mu/W measured at 570 mV, 50/spl deg/C.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2005.859893