Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant t...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems Jg. 11; H. 6; S. 1120 - 1135
Hauptverfasser: Adya, S.N., Markov, I.L.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Piscataway, NJ IEEE 01.12.2003
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Application specific integrated circuits
Applied sciences
Computation
Computational modeling
Context modeling
Design automation
Design engineering
Design. Technologies. Operation analysis. Testing
Electronics
Empirical analysis
Exact sciences and technology
Floorplans
Integrated circuits
Mathematical analysis
Nonhomogeneous media
Operations research
Pins
Representations
Routing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shape
Simulated annealing
Studies
Very large scale integration
physical design
VLSI circuit
Circuit design
hierachical design
Index Terms-Floorplanning
VLSI CAD
System on a chip
Aspect ratio
Algorithm
Implementation
Optimization
Computation time
Integrated circuit layout
Linear combination
Integrated circuit
Simulated annealing
Objective function
Miniaturization
placement
Custom circuit
Computer aided design
ISSN:1063-8210, 1557-9999
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Zusammenfassung:Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.
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ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2003.817546