A family of parallel QR factorization algorithms

Rapid computation of the QR factorization of a matrix is fundamental to many scientific and engineering problems. The paper presents a family of algorithms parameterized by the number of processors available P, arithmetic grain aggregation parameters g1, g2, …, gP, and communication grain aggregatio...

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Veröffentlicht in:Concurrency (Chichester, England.) Jg. 8; H. 6; S. 461 - 473
Hauptverfasser: Meyer, Gerard G.L., Pascale, Mike
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Chichester John Wiley & Sons, Ltd 01.07.1996
ISSN:1040-3108, 1096-9128
Online-Zugang:Volltext
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Zusammenfassung:Rapid computation of the QR factorization of a matrix is fundamental to many scientific and engineering problems. The paper presents a family of algorithms parameterized by the number of processors available P, arithmetic grain aggregation parameters g1, g2, …, gP, and communication grain aggregation parameter h, which computer the QR factorization of a matrix A ∈ Cm × n with minimal latency. The approach is particularly well suited for dedicated distributed memory architectures such as linear arrays of INMOS Transputers, Texas Instruments C40s or Analog Devices 21060s.
Bibliographie:istex:02A466EBA81A94120FF91581687F133C19F866FF
ArticleID:CPE256
ark:/67375/WNG-S0HH44F8-L
SourceType-Scholarly Journals-2
ObjectType-Feature-2
ObjectType-Conference Paper-1
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SourceType-Conference Papers & Proceedings-1
ObjectType-Article-3
ISSN:1040-3108
1096-9128
DOI:10.1002/(SICI)1096-9128(199607)8:6<461::AID-CPE256>3.0.CO;2-H