A Hardware Runtime for Task-Based Programming Models

Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only runtimes introduce relevant overhead when targeting fine-grained tasks, result...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on parallel and distributed systems Vol. 30; no. 9; pp. 1932 - 1946
Main Authors: Tan, Xubin, Bosch, Jaume, Alvarez, Carlos, Jimenez-Gonzalez, Daniel, Ayguade, Eduard, Valero, Mateo
Format: Journal Article Publication
Language:English
Published: New York IEEE 01.09.2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Accelerators
Arquitectura de computadors
Arquitectures paral·leles
Dependence
Energy conservation
Energy saving
Field programmable gate arrays
Fine-grained parallelism
FPGA
Hardware
Heterogeneous task scheduling
Informàtica
Matrius de portes programables per l'usuari
Multicore processing
Multiprocessadors
Multiprocessing
Multiprocessors
Nested tasks
Parallel processing (Electronic computers)
Processament en paral·lel (Ordinadors)
Programming
Runtime
Software
Switched mode power supplies
Task analysis
Task scheduling
Task-based programming models
Task-dependence analysis
Àrees temàtiques de la UPC
ISSN:1045-9219, 1558-2183
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only runtimes introduce relevant overhead when targeting fine-grained tasks, resulting in performance losses. To overcome this drawback, we present a hardware runtime Picos++ that accelerates critical runtime functions such as task dependence analysis, nested task support, and heterogeneous task scheduling. As a proof-of-concept, the Picos++ hardware runtime has been integrated with a compiler infrastructure that supports parallel task-based programming models. A FPGA SoC running Linux OS has been used to implement the hardware accelerated part of Picos++, integrated with a heterogeneous system composed of 4 symmetric multiprocessor (SMP) cores and several hardware functional accelerators (HwAccs) for task execution. Results show significant improvements on energy and performance compared to state-of-the-art parallel software-only runtimes. With Picos++, applications can achieve up to 7.6x speedup and save up to 90 percent of energy, when using 4 threads and up to 4 HwAccs, and even reach a speedup of 16x over the software alternative when using 12 HwAccs and small tasks.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1045-9219
1558-2183
DOI:10.1109/TPDS.2019.2907493