Optimal design of a VLSI processor with spatially and temporally parallel structure
In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to changes of the environment very quickly. Therefore, the development of special‐purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially p...
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| Veröffentlicht in: | Electronics & communications in Japan. Part 3, Fundamental electronic science Jg. 80; H. 8; S. 1 - 10 |
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| Hauptverfasser: | , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
Wiley Subscription Services, Inc., A Wiley Company
01.08.1997
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| Schlagworte: | |
| ISSN: | 1042-0967, 1520-6440 |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to changes of the environment very quickly. Therefore, the development of special‐purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high‐level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(8): 1–10, 1997 |
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| Bibliographie: | ArticleID:ECJC1 istex:C6FD6A0E71CCD97874F666C014F786226701EED2 ark:/67375/WNG-JHW5C9KM-T ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| ISSN: | 1042-0967 1520-6440 |
| DOI: | 10.1002/(SICI)1520-6440(199708)80:8<1::AID-ECJC1>3.0.CO;2-O |