FPGA implementation of low complexity LDPC iterative decoder

Low-density parity-check (LDPC) codes, proposed by Gallager, emerged as a class of codes which can yield very good performance on the additive white Gaussian noise channel as well as on the binary symmetric channel. LDPC codes have gained lots of importance due to their capacity achieving property a...

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Bibliographic Details
Published in:	International journal of electronics Vol. 103; no. 7; pp. 1112 - 1126
Main Authors:	Verma, Shivani, Sharma, Sanjay
Format:	Journal Article
Language:	English
Published:	Abingdon Taylor & Francis 02.07.2016 Taylor & Francis LLC
Subjects:	Algorithms Architecture Channels check-node unit Codes Complexity Decoders Decoding Electrical engineering Error correcting codes iterative decoding algorithms LDPC Message passing parity-check matrix Propagation SMPA
ISSN:	0020-7217, 1362-3060
Online Access:	Get full text
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