Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck

The central unit of a Viterbi decoder is a data-dependent feedback loop which performs an add-compare-select (ACS) operation. This nonlinear recursion is the only bottleneck for a high-speed parallel implementation. A linear scale solution (architecture) is presented which allows the implementation...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on communications Jg. 37; H. 8; S. 785 - 790
Hauptverfasser:	Fettweis, G., Meyr, H.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York, NY IEEE 01.08.1989 Institute of Electrical and Electronics Engineers
Schlagworte:	Applied sciences Coding, codes Computer architecture Decoding Dynamic programming Exact sciences and technology Feedback loop Hardware Information, signal and communications theory Markov processes Recursive estimation Signal and communications theory Systolic arrays Telecommunications and information theory Throughput Viterbi algorithm System architecture Bottleneck Parallel algorithm Flow rate Decoding Systolic network Viterbi decoding
ISSN:	0090-6778
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!