A superlinear speedup region for matrix multiplication

SUMMARYThe realization of modern processors is based on a multicore architecture with increasing number of cores per processor. Multicore processors are often designed such that some level of the cache hierarchy is shared among cores. Usually, last level cache is shared among several or all cores (e...

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Veröffentlicht in:Concurrency and computation Jg. 26; H. 11; S. 1847 - 1868
Hauptverfasser: Gusev, Marjan, Ristov, Sasko
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Blackwell Publishing Ltd 10.08.2014
Schlagworte:
Amdahl's law
Architecture (computers)
Boundaries
cache memory
Gustafson's law
Hardware
Hierarchies
high performance computing
Microprocessors
Multiplication
Multiprocessor
Processors
shared memory multiprocessor
ISSN:1532-0626, 1532-0634
Online-Zugang:Volltext
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Zusammenfassung:SUMMARYThe realization of modern processors is based on a multicore architecture with increasing number of cores per processor. Multicore processors are often designed such that some level of the cache hierarchy is shared among cores. Usually, last level cache is shared among several or all cores (e.g., L3 cache) and each core possesses private low level caches (e.g., L1 and L2 caches). Superlinear speedup is possible for matrix multiplication algorithm executed in a shared memory multiprocessor due to the existence of a superlinear region. It is a region where cache requirements for matrix storage of the sequential execution incur more cache misses than in parallel execution. This paper shows theoretically and experimentally that there is a region, where the superlinear speedup can be achieved. We provide a theoretical proof of existence of a superlinear speedup and determine boundaries of the region where it can be achieved. The experiments confirm our theoretical results. Therefore, these results will have impact on future software development and exploitation of parallel hardware on the basis of a shared memory multiprocessor architecture. Copyright © 2013 John Wiley & Sons, Ltd.
Bibliographie:ArticleID:CPE3102
istex:9C27044DBC4EEA42084C37D18247304FF550B9CD
ark:/67375/WNG-8S4LMK3P-G
ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1532-0626
1532-0634
DOI:10.1002/cpe.3102