Gibraltar: A Reed-Solomon coding library for storage applications on programmable graphics processors

SUMMARY Reed–Solomon coding is a method for generating arbitrary amounts of erasure correction information from original data via matrix–vector multiplication in finite fields. Previous work has shown that modern CPUs are not well‐matched to this type of computation, requiring applications that depe...

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Published in:Concurrency and computation Vol. 23; no. 18; pp. 2477 - 2495
Main Authors: Curry, Matthew L., Skjellum, Anthony, Lee Ward, H., Brightwell, Ron
Format: Journal Article
Language:English
Published: Chichester, UK John Wiley & Sons, Ltd 25.12.2011
Subjects:
Arrays
Central processing units
Coding
Computation
fault olerance
Gibraltar
graphics processors
High speed
Libraries
Processors
Reed-Solomon coding
reliability
storage
ISSN:1532-0626, 1532-0634, 1532-0634
Online Access:Get full text
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Summary:SUMMARY Reed–Solomon coding is a method for generating arbitrary amounts of erasure correction information from original data via matrix–vector multiplication in finite fields. Previous work has shown that modern CPUs are not well‐matched to this type of computation, requiring applications that depend on Reed–Solomon coding at high speeds (such as high‐performance storage arrays) to use hardware implementations. This work demonstrates that high performance is possible with current cost‐effective graphics processing units across a wide range of operating conditions and describes how performance will likely evolve in similar architectures. It describes the characteristics of the graphics processing unit architecture that enable high‐speed Reed–Solomon coding. A high‐performance practical library, Gibraltar, has been prototyped that performs Reed–Solomon coding on graphics processors in a manner suitable for storage arrays, along with applications with similar data resiliency needs. This library enables variably resilient erasure correcting codes to be used in a broad range of applications. Its performance is compared with that of a widely available CPU implementation, and a rationale for its API is presented. Its practicality is demonstrated through a usage example. Copyright © 2011 John Wiley & Sons, Ltd.
Bibliography:National Science Foundation - No. MRI-0821497
ArticleID:CPE1810
ark:/67375/WNG-GHM5WBTN-7
United States Department of Energy - No. DE-FC02-06ER25767
istex:CE7945B98746ABB50326B51AF7F39D7C5C052394
ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
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ISSN:1532-0626
1532-0634
1532-0634
DOI:10.1002/cpe.1810