A low latency SISO with application to broadband turbo decoding

The standard algorithm for computing the soft-inverse of a finite-state machine [i.e., the soft-in/soft-out (SISO) module] is the forward-backward algorithm. These forward and backward recursions can be computed in parallel, yielding an architecture with latency /spl Oscr/(N), where N is the block s...

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Vydané v:IEEE journal on selected areas in communications Ročník 19; číslo 5; s. 860 - 870
Hlavní autori: Beerel, P.A., Chugg, K.M.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.05.2001
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithms
Blocking
Broadband
Computation
Computer architecture
Concurrent computing
Decoding
Delay
Iterative algorithms
Iterative decoding
Recursion
Signal processing algorithms
Throughput
Turbo codes
Very large scale integration
Viterbi algorithm
ISSN:0733-8716, 1558-0008
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Shrnutí:The standard algorithm for computing the soft-inverse of a finite-state machine [i.e., the soft-in/soft-out (SISO) module] is the forward-backward algorithm. These forward and backward recursions can be computed in parallel, yielding an architecture with latency /spl Oscr/(N), where N is the block size. We demonstrate that the standard SISO computation may be formulated using a combination of prefix and suffix operations. Based on well-known tree-structures for fast parallel prefix computations in the very large scale integration (VLSI) literature (e.g., tree adders), we propose a tree-structured SISO that has latency /spl Oscr/(log/sub 2/N). The decrease in latency comes primarily at a cost of area with, in some cases, only a marginal increase in computation. We discuss how this structure could be used to design a very high throughput turbo decoder or, more generally, an iterative detector. Various subwindowing and tiling schemes are also considered to further improve latency.
Bibliografia:ObjectType-Article-2
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ISSN:0733-8716
1558-0008
DOI:10.1109/49.924870