A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders

A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficie...

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Vydáno v:Journal of signal processing systems Ročník 61; číslo 3; s. 329 - 345
Hlavní autoři: Mohsenin, Tinoosh, Baas, Bevan M.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Boston Springer US 01.12.2010
Témata:
Algorithms
Chips
Circuits and Systems
Computer Imaging
Decoders
Decoding
Density
Electrical Engineering
Engineering
Image Processing and Computer Vision
Parity
Pattern Recognition
Pattern Recognition and Graphics
Signal processing
Signal,Image and Speech Processing
Vision
CMOS
65 nm
VLSI
10GBASE-T
LDPC
Low density parity check
Split-Row
Iterative decoder
ISSN:1939-8018, 1939-8115
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Shrnutí:A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method significantly reduces the wire interconnect and decoder complexity and therefore results in fast, small, and high energy efficiency circuits. Three full-parallel decoder chips for a (2,048, 1,723) LDPC code compliant with the 10GBASE-T standard using MinSum normalized, MinSum Split-2, and MinSum Split-4 methods are designed in 65 nm, seven metal layer CMOS. The Split-4 decoder occupies 6.1 mm 2 , operates at 146 MHz, delivers 19.9 Gbps throughput, with 15 decoding iterations. At 0.79 V, it operates at 47 MHz, delivers 6.4 Gbps and dissipates 226 mW. Compared to MinSum normalized, the Split-4 decoder chip is 3.3 times smaller, has a clock rate and throughput 2.5 times higher, is 2.5 times more energy efficient, and has an error performance degradation of 0.55 dB with 15 iterations.
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ISSN:1939-8018
1939-8115
DOI:10.1007/s11265-010-0456-y