Real-time implementation of fast discriminative scale space tracking algorithm

Real-time object tracking is an important step of many modern image processing applications. The efficient hardware design of real-time object tracker must achieve the desired accuracy while satisfying the frame rate requirements for a variety of image sizes. The existing methods of visual tracking...

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Bibliographic Details
Published in:Journal of real-time image processing Vol. 18; no. 6; pp. 2347 - 2360
Main Authors: Walid, Walid, Awais, Muhammad, Ahmed, Ashfaq, Masera, Guido, Martina, Maurizio
Format: Journal Article
Language:English
Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.12.2021
Springer Nature B.V
Subjects:
Algorithms
Computer architecture
Computer Graphics
Computer Science
Computing time
Decomposition
Field programmable gate arrays
Fourier transforms
Image processing
Image Processing and Computer Vision
Multimedia Information Systems
Optical tracking
Original Research Paper
Pattern Recognition
Real time
Reconfigurable hardware
Resource utilization
Signal,Image and Speech Processing
Singular value decomposition
Software
DSST
SVD
QR
DFT
FPGA
Real time
Discriminative correlation filter
ISSN:1861-8200, 1861-8219
Online Access:Get full text
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Summary:Real-time object tracking is an important step of many modern image processing applications. The efficient hardware design of real-time object tracker must achieve the desired accuracy while satisfying the frame rate requirements for a variety of image sizes. The existing methods of visual tracking employ sophisticated algorithms and challenge the capabilities of most embedded architectures. Discriminative scale space tracking is one algorithm that is capable of demonstrating good performance with affordable complexity. It has a high degree of parallelism which can be exploited for efficient implementation of reconfigurable hardware architectures. This paper proposes a real-time implementation of the discriminative scale-space tracker on FPGA for the major blocks. A careful design exploration of core mathematical operations of the tracking algorithm is performed to improve their hardware utilization and timing performance. Among the core functional units optimized in this work, the discrete Fourier transform achieves a computational time improvement of 92% relative to existing works, QR factorization achieves a 2.3 × reduction in resource utilization, and singular value decomposition yields a 3.8 × improvement in processing time. The proposed data path architecture is designed using Vivado HLS tool set and implemented for Zync Zed Board (xc7z020clg484-1). For an input image size of 320 × 240, the proposed architecture achieves a mean 25.38 fps.
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ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-021-01119-6