Asynchronous Event-Driven Clocking and Control in Pipelined ADCs

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many...

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Veröffentlicht in:	IEEE transactions on circuits and systems. I, Regular papers Jg. 68; H. 7; S. 2813 - 2826
Hauptverfasser:	Hershberg, Benjamin, van Liempd, Barend, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Dermit, Davide, Craninckx, Jan
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.07.2021 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	A/D ADC Amplifiers asynchronous clock tree Clocks CMOS Control equipment deep pipeline Delays dynamic Energy conversion efficiency event-driven Figure of merit Generators high speed low power pipeline pipelined ADC Pipelines Power efficiency Quantization (signal) ring amplifier ringamp Robust control Switches Synchronism Topology
ISSN:	1549-8328, 1558-0806
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Abstract	An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.
AbstractList	An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.
Author	Markulic, Nereo Craninckx, Jan Martens, Ewout van Liempd, Barend Dermit, Davide Lagos, Jorge Hershberg, Benjamin
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Cites_doi	10.1109/JSSC.2018.2879923 10.1109/JSSC.2012.2204543 10.1109/MDT.2011.71 10.1109/VLSICircuits18222.2020.9162788 10.1109/JSSC.2011.2143811 10.1049/el.2018.6121 10.1109/CICC.2013.6658443 10.1109/4.726586 10.1109/JSSC.2013.2279571 10.1109/JSSC.2003.819166 10.1109/ISSCC.2004.1332794 10.1109/PrimeAsia.2012.6458655 10.1109/JSSC.2017.2784762 10.1109/JSSC.2021.3053893 10.1109/JSSC.2020.3020194 10.1109/JSSC.2012.2217865 10.1109/JSSC.2018.2889680 10.1109/ISSCC.2019.8662290 10.1109/JSSC.2007.914249 10.1109/JSSC.2011.2143870 10.1109/JSSC.2014.2300199 10.1109/ISSCC19947.2020.9063055 10.1109/JSSC.2020.3044831 10.1109/ISSCC.2019.8662319 10.1109/JSSC.2013.2258814
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SubjectTerms	A/D ADC Amplifiers asynchronous clock tree Clocks CMOS Control equipment deep pipeline Delays dynamic Energy conversion efficiency event-driven Figure of merit Generators high speed low power pipeline pipelined ADC Pipelines Power efficiency Quantization (signal) ring amplifier ringamp Robust control Switches Synchronism Topology
Title	Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
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