Asynchronous Event-Driven Clocking and Control in Pipelined ADCs

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 68; no. 7; pp. 2813 - 2826
Main Authors: Hershberg, Benjamin, van Liempd, Barend, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Dermit, Davide, Craninckx, Jan
Format: Journal Article
Language:English
Published: New York IEEE 01.07.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
A/D
ADC
Amplifiers
asynchronous
clock tree
Clocks
CMOS
Control equipment
deep pipeline
Delays
dynamic
Energy conversion efficiency
event-driven
Figure of merit
Generators
high speed
low power
pipeline
pipelined ADC
Pipelines
Power efficiency
Quantization (signal)
ring amplifier
ringamp
Robust control
Switches
Synchronism
Topology
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.
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content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2021.3077881