Design of high-speed, low-power, and area-efficient FIR filters

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2r is more specially investigated. RADI...

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Bibliographic Details
Published in:IET circuits, devices & systems Vol. 12; no. 1; pp. 1 - 11
Main Authors: Liacha, Ahmed, Oudjida, Abdelkrim K, Ferguene, Farid, Bakiri, Mohammed, Berrandjia, Mohamed L
Format: Journal Article
Language:English
Published: Stevenage The Institution of Engineering and Technology 01.01.2018
John Wiley & Sons, Inc
Subjects:
adders
Adding circuits
Algorithms
CMOS logic circuits
Competition
complementary metal oxide semiconductor technology
Complexity
Cost control
Critical path
digital arithmetic
FIR filter design
FIR filters
Heuristic
lowest adder cost
MCM algorithm
multiple constant multiplication algorithm
Multiplication
RADIX-2r
Research Article
Technology assessment
lowest adder cost
FIR filters
FIR filter design
adders
CMOS logic circuits
digital arithmetic
RADIX-2r
multiple constant multiplication algorithm
MCM algorithm
complementary metal oxide semiconductor technology
ISSN:1751-858X, 1751-8598, 1751-8598
Online Access:Get full text
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Summary:In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2r. The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2r is more specially investigated. RADIX-2r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2r in high order filters.
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ISSN:1751-858X
1751-8598
1751-8598
DOI:10.1049/iet-cds.2017.0058