Automorphism Set Construction for Automorphism Ensemble Decoding With Reduced Delay
The anticipated demands of 6G ultra-reliable low-latency communications (URLLC) call for near-instantaneous data transfers and error-correction efficiency rivaling maximum-likelihood (ML) decoding. Achieving an effective compromise between latency, power consumption, and decoding accuracy is a pivot...
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| Veröffentlicht in: | IEEE open journal of the Communications Society Jg. 6; S. 8625 - 8635 |
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| Hauptverfasser: | , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
IEEE
2025
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 2644-125X, 2644-125X |
| Online-Zugang: | Volltext |
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| Zusammenfassung: | The anticipated demands of 6G ultra-reliable low-latency communications (URLLC) call for near-instantaneous data transfers and error-correction efficiency rivaling maximum-likelihood (ML) decoding. Achieving an effective compromise between latency, power consumption, and decoding accuracy is a pivotal challenge in contemporary coding theory. Polar codes have distinguished themselves by achieving capacity on symmetric memoryless channels. To narrow the gap to ML performance, refined techniques like successive-cancellation list (SCL) decoding have been developed, albeit with a rise in computational burden. More recently, automorphism ensemble (AE) decoding has unlocked parallelization benefits for codes with rich automorphism groups, such as Reed-Muller codes. This paper discusses the reduced-delay AE (RD-AE) decoder, which harnesses a carefully chosen subset of automorphisms to drastically cut decoding latency while allowing a flexible trade-off between speed and error-correction performance. This article is an extended version of research previously introduced at a conference. We discuss key aspects and nuances of the algorithm and its implementation, including: (1) algorithms for selecting automorphism sets to meet specific performance targets, (2) a detailed procedure for combining bits from different permutations, (3) code construction methodologies for RD-AE decoding, and (4) implementation considerations. Furthermore, we explore various scenarios and applications of the proposed algorithm and present simulation results demonstrating significant latency reductions while maintaining error-correction performance. |
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| Bibliographie: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 2644-125X 2644-125X |
| DOI: | 10.1109/OJCOMS.2025.3617311 |