High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resourc...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 68; no. 2; pp. 741 - 750
Main Authors: Wang, Xinyu, Liang, Huaguo, Wang, Yanjie, Yao, Liang, Guo, Yang, Yi, Maoxiang, Huang, Zhengfeng, Qi, Haochen, Lu, Yingchun
Format: Journal Article
Language:English
Published: New York IEEE 01.02.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Ambient temperature
Delays
Electronic design automation
Encryption
Entropy
Field programmable gate arrays
FPGA
Jitter
jitter-latch structure
Numbers
Oscillators
Phase locked loops
Portability
Random numbers
Randomness
STRs
Throughput
TRNG
Vibration
ISSN:1549-8328, 1558-0806
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2020.3037173