XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated...

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Bibliographic Details
Published in:IEEE journal of solid-state circuits Vol. 55; no. 6; pp. 1733 - 1743
Main Authors: Yin, Shihui, Jiang, Zhewei, Seo, Jae-Sun, Seok, Mingoo
Format: Journal Article
Language:English
Published: New York IEEE 01.06.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Accuracy
Analog to digital conversion
Analog to digital converters
Artificial neural networks
Binary weights
CMOS
Complexity theory
Computation
Computer architecture
deep neural networks (DNNs)
Energy conversion efficiency
Energy efficiency
ensemble learning
Hardware
in-memory computing (IMC)
Neural networks
Random access memory
SRAM
Static random access memory
System-on-chip
ternary activations
Transistors
Voltage dividers
ISSN:0018-9200, 1558-173X
Online Access:Get full text
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Summary:We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated on the read bitline (RBL) by simultaneously turning on all 256 rows, essentially forming a resistive voltage divider. The analog RBL voltage is digitized with a column-multiplexed 11-level flash analog-to-digital converter (ADC) at the XNOR-SRAM periphery. XNOR-SRAM is prototyped in a 65-nm CMOS and achieves the energy efficiency of 403 TOPS/W for ternary-XAC operations with 88.8% test accuracy for the CIFAR-10 data set at 0.6-V supply. This marks <inline-formula> <tex-math notation="LaTeX">33\times </tex-math></inline-formula> better energy efficiency and <inline-formula> <tex-math notation="LaTeX">300\times </tex-math></inline-formula> better energy-delay product than conventional digital hardware and also represents among the best tradeoff in energy efficiency and DNN accuracy.
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ISSN:0018-9200
1558-173X
DOI:10.1109/JSSC.2019.2963616