An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures

In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the fi...

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Vydané v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 40; číslo 10; s. 2117 - 2127
Hlavní autori: Dani, Lalit Mohan, Mishra, Neeraj, Bulusu, Anand
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.10.2021
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Accuracy
Capacitance
Design engineering
Design optimization
Effective drive current
Integrated circuit modeling
Layouts
look-up-table (LUT)
Lookup tables
MOS-varactor
near-threshold voltage (NTV) regime
Optimization techniques
Power consumption
Predictive models
process–voltage–temperature (PVT) variation
Simulation
simulation speed
Table lookup
Topology
Transistors
Varactor diodes
Varactors
Voltage controlled oscillators
voltage-controlled ring oscillator (RO)
ISSN:0278-0070, 1937-4151
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Shrnutí:In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current (<inline-formula> <tex-math notation="LaTeX">I_{\mathrm {eff}} </tex-math></inline-formula>) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and <inline-formula> <tex-math notation="LaTeX">I_{\mathrm {eff}} </tex-math></inline-formula> are generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The <inline-formula> <tex-math notation="LaTeX">I_{\mathrm {eff}} </tex-math></inline-formula>-models predict the oscillation frequency (<inline-formula> <tex-math notation="LaTeX">{f}_{OSC} </tex-math></inline-formula>) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- <inline-formula> <tex-math notation="LaTeX">I_{\mathrm {eff}} </tex-math></inline-formula>-capacitance models account for the change in <inline-formula> <tex-math notation="LaTeX">{f}_{OSC} </tex-math></inline-formula>, tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular <inline-formula> <tex-math notation="LaTeX">{f}_{OSC} </tex-math></inline-formula>. Finally, the design methodology ensures that the desired <inline-formula> <tex-math notation="LaTeX">{f}_{OSC} </tex-math></inline-formula> is within the "linear" range of the VCO's-gain due to statistical variation of <inline-formula> <tex-math notation="LaTeX">V_{\mathrm{ th}} </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">V_{\mathrm{ DD}} </tex-math></inline-formula>, etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.
Bibliografia:ObjectType-Article-1
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2020.3037881