Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potential...

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Bibliographic Details
Published in:	IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 6; pp. 2103 - 2113
Main Authors:	Moon, Seungsik, Choe, Jeongwon, Lee, Youngjoo
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.06.2020 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Acceleration Algorithms BCH decoding Computation Deactivation Decoding Delays emerging nonvolatile memory Energy consumption error-correction code High speed Indexes Iterative decoding Iterative methods low-latency processing Memory management Modules Recovery VLSI
ISSN:	1549-8328, 1558-0806
Online Access:	Get full text
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