Low-Power Scalable TSPI: A Modular Off-Chip Network for Edge AI Accelerators

In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to support a modular network structure that facilitates the scalable connection of multiple...

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Published in:IEEE access Vol. 12; pp. 141448 - 141459
Main Authors: Park, Seunghyun, Park, Daejin
Format: Journal Article
Language:English
Published: Piscataway IEEE 2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Accelerator architectures
Accelerators
Algorithms
Computational modeling
Computer architecture
Distributed databases
Edge AI
Edge computing
edge device
Indexes
low power
Low power electronics
Message passing
Modular structures
MPI
Network architecture
off-chip network
Performance evaluation
Power consumption
Random access memory
Scalability
subset mapping algorithm
TSPI
ISSN:2169-3536, 2169-3536
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Abstract In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to support a modular network structure that facilitates the scalable connection of multiple accelerators. The TSPI network employs a subset mapping algorithm for efficient routing and integrates the message passing interface (MPI) protocol to ensure rapid data distribution and aggregation. This modular architecture significantly reduces power consumption and improves processing speed. Experimental results demonstrate that our proposed TSPI network achieves a 54.7% reduction in power consumption and an 82.3% decrease in switching power compared to traditional SPI networks, along with a 23% increase in processing speed when utilizing 16 nodes. These advancements make the TSPI network an effective solution for enhancing AI performance in edge computing environments.
AbstractList In this paper, we present a novel off-chip network architecture, the Tile Serial Peripheral Interface (TSPI), designed for low-power, scalable edge AI accelerators. Our approach modifies the conventional SPI to support a modular network structure that facilitates the scalable connection of multiple accelerators. The TSPI network employs a subset mapping algorithm for efficient routing and integrates the message passing interface (MPI) protocol to ensure rapid data distribution and aggregation. This modular architecture significantly reduces power consumption and improves processing speed. Experimental results demonstrate that our proposed TSPI network achieves a 54.7% reduction in power consumption and an 82.3% decrease in switching power compared to traditional SPI networks, along with a 23% increase in processing speed when utilizing 16 nodes. These advancements make the TSPI network an effective solution for enhancing AI performance in edge computing environments.
Author Park, Daejin
Park, Seunghyun
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SubjectTerms Accelerator architectures
Accelerators
Algorithms
Computational modeling
Computer architecture
Distributed databases
Edge AI
Edge computing
edge device
Indexes
low power
Low power electronics
Message passing
Modular structures
MPI
Network architecture
off-chip network
Performance evaluation
Power consumption
Random access memory
Scalability
subset mapping algorithm
TSPI
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Title Low-Power Scalable TSPI: A Modular Off-Chip Network for Edge AI Accelerators
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