Parallel Algorithms for Testing Finite State Machines:Generating UIO Sequences

This paper describes an efficient parallel algorithm that uses many-core GPUs for automatically deriving Unique Input Output sequences (UIOs) from Finite State Machines. The proposed algorithm uses the global scope of the GPU's global memory through coalesced memory access and minimises the tra...

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Vydané v:IEEE transactions on software engineering Ročník 42; číslo 11; s. 1077 - 1091
Hlavní autori: Hierons, Robert M., Turker, Uraz Cengiz
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.11.2016
IEEE Computer Society
Predmet:
Algorithm design and analysis
Algorithms
Automata
Automation
finite state machine
general purpose graphics processing units
Graphics processing units
Input output
Software algorithms
Software engineering
Software engineering/software/program verification
software engineering/test design
software engineering/testing and debugging
Studies
Testing
unique input output sequence generation
User interface
ISSN:0098-5589, 1939-3520
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Shrnutí:This paper describes an efficient parallel algorithm that uses many-core GPUs for automatically deriving Unique Input Output sequences (UIOs) from Finite State Machines. The proposed algorithm uses the global scope of the GPU's global memory through coalesced memory access and minimises the transfer between CPU and GPU memory. The results of experiments indicate that the proposed method yields considerably better results compared to a single core UIO construction algorithm. Our algorithm is scalable and when multiple GPUs are added into the system the approach can handle FSMs whose size is larger than the memory available on a single GPU.
Bibliografia:SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ISSN:0098-5589
1939-3520
DOI:10.1109/TSE.2016.2539964