Automatic Processor Customization for Zero-Overhead Online Software Verification

The PSL-to-Verilog (P2V) compiler can translate a set of assertions about a block-structured software program into a hardware design to be executed concurrently with the program. The assertions validate the correctness of the software program without altering the program's temporal behavior in...

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Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 16; číslo 10; s. 1346 - 1357
Hlavní autori:	Hong Lu, Forin, A.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.10.2008 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Assertion-based verification Behavior Computer programs Dynamical systems Dynamics eMIPS Field programmable gate arrays Hardware Intrusion detection Microprocessors monitor online Operating systems Program processors Program verification (computers) property specification language (PSL) PSL-to-Verilog (P2V) Real time systems Software Software debugging Software systems Software testing Specification languages temporal logic Verilog Very large scale integration
ISSN:	1063-8210, 1557-9999
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